SH7763 Datasheet, PDF (1296/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
(2) Reception in Master Mode
Figure 29.10 shows an example of settings and operation for master mode reception.
No.
Flow Chart
Start
1
Set SIMDR, SISCR,
SIRDAR, SICDAR, and SIFCTR
2
Set the SCKE bit in SICTR to 1
SIOF Settings
Set operating mode, serial clock,
slot positions for receive data,
slot position for control data, and
FIFO request threshold value
Set operation start for baud rate
generator
SIOF Operation
3
Start SIOFSCK output
Output serial clock
4
Set the FSE and RXE bits
in SICTR to 1
Store SIOFRXD receive data in SIRDR
5
synchronously with SIOF_SYNC
Set the start for frame synchronous
signal output and enable
reception
Output frame synchronous
signal
Issue receive transfer
request according to the
receive FIFO threshold
value
6
RDREQ = 1? ^No
Yes
Reception
7
Read SIRDR
Read receive data
Transfer
No
ended?
8
Yes
Clear the RXE bit in SICTR to 0
End
Set to disable reception
End reception
Figure 29.10 Example of Receive Operation in Master Mode
Rev. 1.00 Oct. 01, 2007 Page 1230 of 1956
REJ09B0256-0100