SH7763 Datasheet, PDF (1571/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
Bit Bit Name Initial Value R/W Description
6
EP1 FULL 0
R EP1 (Bulk-out) FIFO Full
[Setting condition]
The FIFO buffer of EP1 has a dual-buffer
configuration, and this bit is set when at least one of
the FIFO buffer is full.
[Setting conditions]
• When reset
• When both FIFO buffers are empty.
Note: EP1 FULL is a status bit, and cannot be
cleared.
5
EP2 TR 0
R/W EP2 (Bulk-in) Transfer Request
[Setting condition]
When an IN token is received from the host to EP2
and both of FIFO buffers are empty.
[Clearing conditions]
• When reset
• When 0 is written to by CPU
4
EP2
1
EMPTY
R EP2 (Bulk-in) FIFO Empty
[Setting conditions]
• When reset
• The FIFO buffer of EP2 has a dual-buffer
configuration, and this bit is set when at least one
of the FIFO buffer is empty.
[Clearing condition]
When both of FIFO buffers are not empty.
Note: EP2 EMPTY is a status bit, and cannot be
cleared.
Rev. 1.00 Oct. 01, 2007 Page 1505 of 1956
REJ09B0256-0100