SH7763 Datasheet, PDF (1374/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 31 Multimedia Card Interface (MMCIF)
31.3.11 Card Status Register (CSTR)
CSTR indicates the MMCIF status during command sequence execution.
Bit: 7
6
5
4
3
2
1
BUSY
FIFO_
FULL
FIFO_
EMPTY
CWRE
DTBUSY
DTBUSY_
TU
—
Initial value: 0
0
0
0
0—0
R/W: R
R
R
R
R
R
R
0
REQ
0
R
Initial
Bit
Bit Name Value R/W Description
7
BUSY
0
R
Command Busy
Indicates command execution status. When the
CMDOFF bit in OPCR is set to 1, this bit is cleared to 0
because the MMCIF command sequence is aborted.
0: Idle state waiting for a command, or data busy state.
1: Command sequence execution in progress.
6
FIFO_FULL 0
R
FIFO Full
This bit is set to 1 when the FIFO becomes full while
data is being received, and cleared to 0 when
RD_CONTI is set to 1 or the command sequence is
completed.
0: The FIFO is empty.
1: The FIFO is full.
5
FIFO_EMPTY 0
R
FIFO Empty
This bit is set to 1 when the FIFO becomes empty while
data is being sent, and cleared to 0 when DATAEN is
set to 1 or the command sequence is completed.
Indicates whether the FIFO holds data or not.
0: The FIFO includes data.
1: The FIFO is empty.
Rev. 1.00 Oct. 01, 2007 Page 1308 of 1956
REJ09B0256-0100