SH7763 Datasheet, PDF (149/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 4 Pipelining
(3-1) Load/store: 1 issue cycle
MOV.[BWL], MOV.[BWL] @(d,GBR)
I1
I2
ID S1 S2 S3 WB
(3-2) AND.B, OR.B, XOR.B, TST.B: 3 issue cycles
I1
I2
ID S1 S2 S3 WB
ID
ID E1S1 E2S2 E3S3 WB
(3-3) TAS.B: 4 issue cycles
I1
I2
ID S1 S2 S3 WB
ID E1S1 E2S2 E3S3 WB
ID
ID E1S1 E2S2 E3S3 WB
(3-4) PREF, OCBI, OCBP, OCBWB, MOVCA.L, SYNCO: 1 issue cycle
I1
I2
ID S1 S2 S3 WB
(3-5) LDTLB: 1 issue cycle
I1
I2
ID
E1s1 E2s2 E3s3 WB
(3-6) ICBI: 8 issue cycles + 5 cycles + 3 branch cycle
I1 I2 ID s1 s2 s3 WB
ID
ID
ID
ID
5 cycles (min.)
(3-7) PREFI: 5 issue cycles + 5 cycles + 3 branch cycle
I1
I2
ID s1 s2
s3 WB
ID E1s1 E2s2 E3s3 WB
ID E1s1 E2s2 E3s3 WB
ID E1s1 E2s2 _{E3s3 WB}
ID E1s1 E2s2 E3s3 WB
(I1) (I2) (ID)
(Branch to the next instruction of ICBI.)
(3-8) MOVLI.L: 1 issue cycle
I1
I2
ID S1
(3-9) MOVCO.L: 1 issue cycle
I1
I2
ID S1
(3-10) MOVUA.L: 2 issue cycles
I1
I2
ID S1
5 cycles (min.)
S2 S3 WB
ID E1s1 E2s2 E3s3 WB
ID E1s1 E2s2 E3s3 WB
ID E1s1 E2s2 E3s3 WB
(I1) (I2) (ID)
(Branch to the next instruction of PREFI.)
S2 S3 WB
S2 S3 WB
S1 S2 S3 WB
Figure 4.2 Instruction Execution Patterns (3)
Rev. 1.00 Oct. 01, 2007 Page 83 of 1956
REJ09B0256-0100