SH7763 Datasheet, PDF (1283/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
29.4 Operation
29.4.1 Serial Clocks
(1) Master/Slave Modes
The following modes are available as the SIOF clock mode.
• Slave mode: SIOF_SCK, SIOF_SYNC input
• Master mode: SIOF_SCK, SIOF_SYNC output
(2) Baud Rate Generator
In SIOF master mode, the baud rate generator (BRG) is used to generate the serial clock. The
division ratio is from 1/1 to 1/1024.
Note that, when using master clock directly as the serial clock without division by BRG (division
ratio: 1/1), the MSIMM bit in SISCR should be set to 1.
Figure 29.2 shows connections for supply of the serial clock.
Baud rate generator
1/1 to 1/1024
Master clock
Master clock
Pre-
scalar ^Divider
SIOF_MCLK
Pck
Timing
control
SIOF_SCK
Figure 29.2 Serial Clock Supply
Table 29.5 shows an example of serial clock frequency.
SCKE
Master
Rev. 1.00 Oct. 01, 2007 Page 1217 of 1956
REJ09B0256-0100