SH7763 Datasheet, PDF (506/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
(MCLK)
MCLK
CKE
Command
MA9-0
MA13-11
MA10
BA1-0
MCS
MRAS
MCAS
MWE
MDQS
MDA
MDQM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
ACT
READA
Row
t_RC (SRC = 011)
t_RCD (SRCD = 1)
t_RAS (SRAS = 000)
Col 0
Row
Bank
Bank
ACT
t_RP (SRP = 0)
Row
Row
Bank
Hi-Z
CL = 2.5
D0 D1
Hi-Z
Figure 12.7 Basic DDRIF Timing (1 Burst Read: 1, 2, 4, or 8 Bytes; With Auto-Precharge)
Rev. 1.00 Oct. 01, 2007 Page 440 of 1956
REJ09B0256-0100