SH7763 Datasheet, PDF (61/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Table 20.13 Up/Down-Count Conditions in Phase Counting Mode 4.................................. 731
Section 21 Compare Match Timer (CMT)
Table 21.1 Register Configuration.......................................................................................... 735
Table 21.2 Register State in Each Operating Mode ................................................................ 736
Section 22 Realtime Clock (RTC)
Table 22.1 RTC Pins............................................................................................................... 747
Table 22.2 Register Configuration.......................................................................................... 748
Table 22.3 Register State in Each Operating Mode ................................................................ 749
Table 22.4 Crystal Oscillator Circuit Constants (Recommended Values) .............................. 767
Table 22.5 Interrupt source and request generating order....................................................... 768
Section 23 Gigabit Ethernet Controller (GETHER)
Table 23.1 Pin Configuration.................................................................................................... 81
Table 23.2 Register Configuration............................................................................................ 86
Table 23.3 Register States in Each Operating Mode ................................................................ 94
Table 23.4 Relay Frame Process (Without CAM) .................................................................. 264
Table 23.5 Receive Frame Processing .................................................................................... 266
Table 23.6 Relay Frame Process (With CAM) ....................................................................... 266
Table 23.7 List of GETHER Interrupts................................................................................... 271
Section 25 Stream Interface (STIF)
Table 25.1 Pin Configuration.................................................................................................. 985
Table 25.2 Register Configuration.......................................................................................... 986
Table 25.3 Register States in Each Operating Mode .............................................................. 987
Section 26 I²C Bus Interface (IIC)
Table 26.1 Pin Configuration.................................................................................................... 80
Table 26.2 Register Configuration............................................................................................ 80
Table 26.3 Register State in Each Operating Mode .................................................................. 82
Table 26.4 Suggested Settings for CDF and SCGD ................................................................. 97
Table 26.5 Description on Symbols of I²C Bus Data Format ................................................. 100
Section 27 Serial Communication Interface with FIFO (SCIF)
Table 27.1 Pin Configuration................................................................................................ 1051
Table 27.2 Register Configuration (1) .................................................................................. 1052
Table 27.3 Register State in Each Operating Mode .............................................................. 1053
Table 27.4 SCSMR Settings ................................................................................................. 1069
Table 27.5 SCSMR Settings for Serial Transfer Format Selection....................................... 1079
Table 27.6 SCSMR and SCSCR Settings for SCIF Clock Source Selection........................ 1079
Table 27.7 Serial Transfer Formats (Asynchronous Mode).................................................. 1081
Table 27.8 SCIF Interrupt Sources ....................................................................................... 1100
Rev. 1.00 Oct. 01, 2007 Page lxi of lxvi