SH7763 Datasheet, PDF (1068/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 Stream Interface (STIF)
25.3.1 Mode Registers 0, 1 (STIMDR0, STIMDR1)
STIMDR sets the STIF operating mode and clock definition for stream data
transmission/reception.
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
−
MD[2:0]
− − − PLEN − − − STMP[1:0] − WORK[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R R R R/W R R R/W R/W R R R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
− − − CKSL
CKDV[1:0]
− − REQ
EN
−
FRC[1:0] STRB REQ VLD STAT
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R R/W R/W R R R R/W R R R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
31

0
30 to 28 MD[2:0] 000
27 to 25 
All 0
24
PLEN
0
23, 22 
All 0
R/W Description
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Stream Data Transfer Interface
000: Clock valid reception
010: Strobe reception
100: Clock valid transmission
101: Strobe transmission
Other than above: Setting prohibited
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Transmit/Receive Packet Length
Sets the packet length of the stream data to be
transmitted or received.
0: Packet length is 188 bytes
1: Packet length is 192 bytes
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1002 of 1956
REJ09B0256-0100