SH7763 Datasheet, PDF (471/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
11.5.9 Bus Arbitration
This LSI is provided with a bus arbitration function that grants the bus to an external device when
it makes a bus request.
This bus arbitration supports master mode. In master mode the bus is held on a constant basis, and
is released to another device in response to a bus request. The bus goes to the high-impedance
state when not being held and it is possible to connect an external device that issues bus requests.
In the following description, an external device that issues bus requests is also referred to as a
slave.
This LSI has three internal bus masters: the CPU, DMAC, and PCIC. In addition to these are bus
requests from external devices. If requests occur simultaneously, priority is given, in high-to-low
order, to a bus request from an external device, the PCIC, the DMAC, and the CPU.
To prevent incorrect operation of connected devices when the bus is transferred between master
and slave, all bus control signals are negated before the bus is released. When mastership of the
bus is received, also, bus control signals begin driving the bus from the negated state. Since
signals are driven to the same value by the master and slave exchanging the bus, output buffer
collisions can be avoided. By turning off the output buffer on the side releasing the bus, and
turning on the output buffer on the side receiving the bus, simultaneously with respect to the bus
control signals, it is possible to eliminate the signal high-impedance period. It is not necessary to
provide the pull-up resistors usually inserted in these control signal lines to prevent incorrect
operation due to external noise in the high-impedance state.
Bus transfer is executed between bus cycles.
When the bus release request signal (BREQ) is asserted, this LSI releases the bus as soon as the
currently executing bus cycle ends, and outputs the bus use permission signal (BACK). However,
bus release is not performed during multiple bus cycles generated because the data bus width is
smaller than the access size (for example, when performing longword access to 8-bit bus width
memory) or during a 32-byte transfer such as a cache fill or write-back. In addition, bus release is
not performed between read and write cycles during execution of a TAS instruction, or between
read and write cycles when DMAC dual address transfer is executed. When BREQ is negated,
BACK is negated and use of the bus is resumed.
As the CPU in this LSI is connected to cache memory by a dedicated internal bus, reading from
cache memory can still be carried out when the bus is being used by another bus master inside or
outside this LSI. When writing from the CPU, an external write cycle is generated when write-
through has been set for the cache in this LSI, or when an access is made to a cache-off area.
There is consequently a delay until the bus is returned.
Rev. 1.00 Oct. 01, 2007 Page 405 of 1956
REJ09B0256-0100