SH7763 Datasheet, PDF (1495/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 34 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value R/W Description
9 (cont.) PDTA
0
R/W • DWL = 010, 011, 100, 101 (with a data word length
of 18, 20, 22 or 24 bits), PDTA = 0 (left-aligned)
The data bits used in SSIRDR or SSITDR are the
following:
Bits 31 down to (32 minus the number of bits in the
data word length specified by DWL).
That is, If DWL = 011, the data word length is 20 bits;
therefore, bits 31 to 12 in either SSIRDR or SSITDR are
used. All other bits are ignored or reserved.
• DWL = 010, 011, 100, 101 (with a data word length
of 18, 20, 22 or 24 bits), PDTA = 1 (right-aligned)
The data bits used in SSIRDR or SSITDR are the
following:
Bits (the number of bits in the data word length
specified by DWL minus 1) to 0
i.e. if DWL = 011, then DWL = 20 and bits 19 to 0 are
used in either SSIRDR or SSITDR. All other bits are
ignored or reserved.
• DWL = 110 (with a data word length of 32 bits), the
PDTA setting is ignored.
All data bits in SSIRDR or SSITDR are used on the
audio serial bus.
8
DEL
0
R/W Serial Data Delay
0: 1 clock cycle delay between SSI_WS and
SSI_SDATA
1: No delay between SSI_WS and SSI_SDATA
7

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1429 of 1956
REJ09B0256-0100