SH7763 Datasheet, PDF (137/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 3 Instruction Set
Table 3.7 Shift Instructions
Instruction
ROTL Rn
ROTR Rn
ROTCL Rn
ROTCR Rn
SHAD Rm,Rn
SHAL
SHAR
SHLD
Rn
Rn
Rm,Rn
SHLL Rn
SHLR Rn
SHLL2 Rn
SHLR2 Rn
SHLL8 Rn
SHLR8 Rn
SHLL16 Rn
SHLR16 Rn
Operation
Instruction Code Privileged T Bit
T ← Rn ← MSB
0100nnnn00000100 —
MSB
LSB → Rn → T
0100nnnn00000101 —
LSB
T ← Rn ← T
0100nnnn00100100 —
MSB
T → Rn → T
0100nnnn00100101 —
LSB
When Rm ≥ 0, Rn << Rm → Rn 0100nnnnmmmm1100 —
—
When Rm < 0, Rn >> Rm →
[MSB → Rn]
T ← Rn ← 0
0100nnnn00100000 —
MSB
MSB → Rn → T
0100nnnn00100001 —
LSB
When Rm ≥ 0, Rn << Rm → Rn 0100nnnnmmmm1101 —
—
When Rm < 0, Rn >> Rm →
[0 → Rn]
T ← Rn ← 0
0100nnnn00000000 —
MSB
0 → Rn → T
0100nnnn00000001 —
LSB
Rn << 2 → Rn
0100nnnn00001000 —
—
Rn >> 2 → Rn
0100nnnn00001001 —
—
Rn << 8 → Rn
0100nnnn00011000 —
—
Rn >> 8 → Rn
0100nnnn00011001 —
—
Rn << 16 → Rn
0100nnnn00101000 —
—
Rn >> 16 → Rn
0100nnnn00101001 —
—
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Rev. 1.00 Oct. 01, 2007 Page 71 of 1956
REJ09B0256-0100