SH7763 Datasheet, PDF (54/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 39 D/A Converter (DAC)
Figure 39.1 Block Diagram of D/A Converter ......................................................................... 1673
Figure 39.2 D/A Converter Operation Example ....................................................................... 1677
Section 41 User Break Controller (UBC)
Figure 41.1 Block Diagram of UBC......................................................................................... 1760
Figure 41.2 Flowchart of User Break Debugging Support Function ........................................ 1790
Section 42 User Debugging Interface (H-UDI)
Figure 42.1 H-UDI Block Diagram .......................................................................................... 1798
Figure 42.2 Sequence for switching from Boundary-Scan TAP Controller to H-UDI............. 1801
Figure 42.3 TAP Controller State Transitions .......................................................................... 1823
Figure 42.4 H-UDI Reset.......................................................................................................... 1824
Section 43 Electrical Characteristics
Figure 43.1 Power-On and Power-Off Timing ......................................................................... 1827
Figure 43.2 EXTAL Clock Input Timing ................................................................................. 1835
Figure 43.3 CLKOUT Clock Output Timing (1)...................................................................... 1835
Figure 43.4 CLKOUT Clock Output Timing (2)...................................................................... 1836
Figure 43.5 Power-On Oscillation Settling Time ..................................................................... 1836
Figure 43.6 PLL Synchronization Settling Time ...................................................................... 1837
Figure 43.7 Oscillation Settling Time on Return from Standby NMI or IRQ .......................... 1837
Figure 43.8 Reset Input Timing................................................................................................ 1837
Figure 43.9 Control Signal Timing........................................................................................... 1838
Figure 43.10 Pin Drive Timing in Standby Mode .................................................................... 1839
Figure 43.11 SRAM Bus Cycle: Basic Bus Cycle (No Wait) .................................................. 1841
Figure 43.12 SRAM Bus Cycle: Basic Bus Cycle (One Wait only by Software) .................... 1842
Figure 43.13 SRAM Bus Cycle: Basic Bus Cycle (One Wait by Software +
One Wait by RDY, RDY Signal is Synchronous Input) ..................................... 1843
Figure 43.14 SRAM Bus Cycle: Basic Bus Cycle (No Wait, No Address Setup/
Hold Time Insertion, RDS = 1, RDH = 0, WTS = 1, WTH = 1) ........................ 1844
Figure 43.15 Burst ROM Bus Cycle (No Wait) ....................................................................... 1845
Figure 43.16 Burst ROM Bus Cycle (1st Data: One Wait by Software +
One Wait by RDY; 2nd/3rd/4th Data: One Wait only by software) .................. 1846
Figure 43.17 Burst ROM Bus Cycle (No Wait, No Address Setup/Hold Time Insertion,
RDS = 1, RDH = 0) ............................................................................................ 1847
Figure 43.18 Burst ROM Bus Cycle (One Wait by Software + One Wait by RDY) ............... 1848
Figure 43.19 PCMCIA Memory Bus Cycle ............................................................................. 1849
Figure 43.20 PCMCIA I/O Bus Cycle...................................................................................... 1850
Figure 43.21 PCMCIA I/O Bus Cycle (TEDA/TEDB = 1, TEHA/TEHB = 1,
IW/PCIW = 1, Dynamic Bus Sizing).................................................................. 1851
Figure 43.22 MPX Basic Bus Cycle: Read............................................................................... 1852
Rev. 1.00 Oct. 01, 2007 Page liv of lxvi