SH7763 Datasheet, PDF (1041/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
Table 23.7 List of GETHER Interrupts
Interrupt Interrupt Source
Transmit/
receive
interrupt for
port 0
(GEINT0)
Write-back completed
Transmit underflow frame write-back
completed
Receive underflow frame write-back
completed
Transmission abort detection
Reception abort detection
Receive frame counter overflow
E-MAC status register source
Frame transmission completed
Transmit descriptor empty
Transmit FIFO underflow
Frame reception
Receive descriptor empty
Receive FIFO overflow
Detect Loss of Carrier
Delayed Collision Detect
Transmit Retry Over
Interrupt Generation
Register and Bit Timing
EESR0.TWB
After write-back
EESR0.TUC
After write-back
EESR0.ROC
After write-back
EESR0.TABT
EESR0.RABT
EESR0.RFCOF
EESR0.ECI
EESR0.TUC
EESR0.TDE
EESR0.TFUF
EESR0.FR
EESR0.RDE
EESR0.RFOF
EESR0.DLC
EESR0.CD
EESR0.TRO
After write-back
After write-back
When the interrupt
source is detected
When the interrupt
source is detected
After write-back
When the interrupt
source is detected
When the interrupt
source is detected
After write-back
When the interrupt
source is detected
When the interrupt
source is detected
When the interrupt
source is detected
When the interrupt
source is detected
When the interrupt
source is detected
Rev. 1.00 Oct. 01, 2007 Page 975 of 1956
REJ09B0256-0100