SH7763 Datasheet, PDF (1370/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 31 Multimedia Card Interface (MMCIF)
31.3.8 Operation Control Register (OPCR)
OPCR aborts command operation, and suspends or continues data transfer.
Bit: 7
6
5
4
3
2
1
0
CMD
OFF
—
RD_
CONTI
DATEN
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R R/W R/W R R R R
Initial
Bit
Bit Name Value R/W Description
7
CMDOFF 0
R/W Command Off
Aborts all command operations (MMCIF command
sequence) when 1 is written to it after a command is
transmitted. This bit is then cleared by hardware.
Write enabled period: From command transmission
completion to command sequence end
Write 0: Operation is not affected.
Write 1: Command sequence is forcibly aborted.
6
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
5
RD_CONTI 0
R/W Read Continue
This bit is cleared by hardware when 1 is written and
the MMCIF resumes data read.
Read data reception is resumed while the sequence
has been halted by FIFO full or termination of block
reading in multiblock read.
Write enabled period: While read data reception is
halted
Write 0: Operation is not affected.
Write 1: Resumes read data reception.
Rev. 1.00 Oct. 01, 2007 Page 1304 of 1956
REJ09B0256-0100