SH7763 Datasheet, PDF (252/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 6 Memory Management Unit (MMU)
6.8 Usage Notes
When using an LDTLB instruction instead of software to a value to the MMUCR. URC,
execute 1 or 2 below.
1. In 29-bit address mode, follow A. and B. below. In 32-bit address mode, follow A. through B.
below.
A. Place the TLB miss exception handling routine*¹ only in the P1 or P2 area so that all the
instruction accesses*³ in the TLB miss exception handling routine should occur solely in
the P1 or P2 area.
B. Use only one page of the PMB for instruction accesses*³ in the TLB miss exception
handling routine*¹. In 32-bit address mode, do not place them in the last 64 bytes of a page
of the PMB.
C. In 32-bit address mode, obey 1 and 2 below when recording information in the UTLB in
the MMU-related exception*² handling routine.
a. If a TLB miss exception occurs, do not record the page, in which the exception has
occurred, in the UTLB using the following two operations.
- Specifies the protection key data that causes a protection violation exception upon re-
execution of the instruction that has caused the TLB miss exception and records the
page, in which the TLB miss exception has occurred, in the UTLB.
- Specifies the protection key data that does not cause a protection violation exception
in the protection violation exception handling routine to record the page in the UTLB
and re-executes the instruction that has caused the protection violation exception.
b. Exclude the pages for which software has once set 1 to the dirty bit upon occurrence of
an initial page write exception and intentionally deleted from the TLB or set 0 to the
dirty bit.
D. Do not make an attempt to execute the FDIV or FSQRT instruction in the MMU-related
exception handling routine.
2. If a TLB miss exception occurs, add 1 to MMUCR.URC before executing an LDTLB
instruction.
Notes: 1. An exception handling routine is an entire set of instructions that are executed from the
address (VBR + offset) upon occurrence of an exception to the RTE for returning to the
original program or to the RTE delay slot.
2. MMU-related exceptions are: instruction TLB miss exception, instruction TLB miss
protection violation exception, data TLB miss exception, data TLB protection violation
exception, and initial page write exception.
3. Instruction accesses include the PREFI and ICBI instructions.
Rev. 1.00 Oct. 01, 2007 Page 186 of 1956
REJ09B0256-0100