SH7763 Datasheet, PDF (270/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 7 Caches
7.5 Cache Operation Instruction
7.5.1 Coherency between Cache and External Memory
Coherency between cache and external memory should be assured by software. In this LSI, the
following six instructions are supported for cache operations. Details of these instructions are
given in the Programming Manual.
• Operand cache invalidate instruction: OCBI @Rn
Operand cache invalidation (no write-back)
• Operand cache purge instruction: OCBP @Rn
Operand cache invalidation (with write-back)
• Operand cache write-back instruction: OCBWB @Rn
Operand cache write-back
• Operand cache allocate instruction: MOVCA.L R0,@Rn
Operand cache allocation
• Instruction cache invalidate instruction: ICBI @Rn
Instruction cache invalidation
• Operand access synchronization instruction: SYNCO
Wait for data transfer completion
The operand cache can receive "PURGE" and "FLUSH" transaction from SuperHyway bus to
control the cache coherency. Since the address used by the PURGE and FLUSH transaction is a
physical address, the following restrictions occur to avoid cache synonym problem in MMU
enable mode.
• 1 Kbyte page size cannot be used.
Rev. 1.00 Oct. 01, 2007 Page 204 of 1956
REJ09B0256-0100