SH7763 Datasheet, PDF (1308/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 30 SIM Card Module (SIM)
Figure 30.1 shows a block diagram of the smart card interface.
Module data bus
Peripheral bus
SIM_D
SCRDR
SCTDR
SCRSR
Parity check
SCTSR
Parity
generation
SCSMR
SCSCR
SCSSR
SCSCMR
SCSC2R
SCWAIT
SCGRD
SCBRR
SCSMPL
Baud rate
generator
SIM_CLK
SIM_RST
Serial clock
ERI
TXI
RXI
TEI
Receive data full
Transmit data empty
[Legend]
SCSCMR : Smart card mode register
SCRSR : _{Receive shift register}
SCRDR : Receive data register
SCTSR : Transmit shift register
SCTDR : Transmit dara register
SCSMR : Serial mode register
SCSCR : Serial control register
SCSC2R : Serial control 2 register
SCSSR : Serial status register
SCBRR : _{Bit rate register}
SCWAIT : Wait time register
SCGRD : Guard extension register
SCSMPL :Sampling register
Figure 30.1 Smart Card Interface
Pck0
interrupt
controller
DMA controller
Rev. 1.00 Oct. 01, 2007 Page 1242 of 1956
REJ09B0256-0100