SH7763 Datasheet, PDF (326/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
9.3.10 Interrupt mask clear register 2 (INTMSKCLR2)
INTMSKCLR2 is 32-bit write-only registers that clear the mask settings for IRL interrupt
requests. An undefined value is read.
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
− IC015 ^IC014 IC013 IC012 IC011 IC010 ^{IC009 IC008 IC007 IC006} IC005 IC004 IC003 IC002 IC001
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
Bit:
Initial value:
R/W:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
− IC115 IC114 IC113 IC112 IC111 IC110 IC109 IC108 IC107 IC106 IC105 IC104 IC103 IC102 IC101
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
Initial
Bit
Bit Name Value R/W Description
31
IC015
0
30
IC014
0
29
IC013
0
28
IC012
0
R/W Clears masking of an
interrupt request when
IRL[3:0] = LLLL (H'0).
R/W Clears masking of an
interrupt request when
IRL[3:0] = LLLH (H'1).
R/W Clears masking of an
interrupt request when
IRL[3:0] = LLHL (H'2).
R/W Clears masking of an
interrupt request when
IRL[3:0] = LLHH (H'3).
[When reading]
An undefined value is
read.
[When writing]
0: Invalid
1: Clears the
corresponding interrupt
mask (Interrupts are
enabled)
27
IC011
0
R/W Clears masking of an
interrupt request when
IRL[3:0] = LHLL (H'4).
26
IC010
0
R/W Clears masking of an
interrupt request when
IRL[3:0] = LHLH (H'5).
25
IC009
0
R/W Clears masking of an
interrupt request when
IRL[3:0] = LHHL (H'6).
24
IC008
0
R/W Clears masking of an
interrupt request when
IRL[3:0] = LHHH (H'7).
Rev. 1.00 Oct. 01, 2007 Page 260 of 1956
REJ09B0256-0100