SH7763 Datasheet, PDF (1510/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 34 Serial Sound Interface (SSI)
(7) Configuration Fields - Signal Format Fields
There are several more configuration bits in non-compressed mode which will now be
demonstrated. These bits are NOT mutually exclusive, however some configurations will probably
not be useful for any other device.
They are demonstrated by referring to the following basic sample format shown in figure 34.9.
SWL = 6 bits (not attainable in SSI module, demonstration only)
DWL = 4 bits (not attainable in SSI module, demonstration only)
CHNL = 00, SCKP = 0, SWSP = 0, SPDP = 0, SDTA = 0, PDTA = 0, DEL = 0, MUEN = 0
4-bit data samples continuously written to SSITDR are transmitted onto the serial audio bus.
SSI_SCK
SSI_WS
1st channel
2nd channel
SSI_SDATA TD28 0 0 TD31 TD30 TD29 TD28 0 0 TD31 TD30 TD29 TD28 0 0 TD31
Key for this and following diagrams:
Arrow head indicates sampling point of receiver
TDn
Bit n in SSITDR
0
means a low level on the serial bus (padding or mute)
1
means a high level on the serial bus (padding)
Figure 34.9 Basic Sample Format
(Transmit Mode with Example System/Data Word Length)
Rev. 1.00 Oct. 01, 2007 Page 1444 of 1956
REJ09B0256-0100