SH7763 Datasheet, PDF (1790/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 40 General Purpose I/O (GPIO)
40.2.19 Port D Data Register (PDDR)
PDDR is an 8-bit readable/writable register that stores port D data.
Bit: 7
6
5
4
3
2
1
0
PD7DT PD6DT PD5DT PD4DT PD3DT PD2DT PD1DT PD0DT
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name value R/W Description
7
PD7DT
0
R/W Each of these bits stores output data for the
6
PD6DT
0
R/W ^{corresponding pin that is used as a general output port.}
If the port is read, the value of the corresponding bit in
5
PD5DT
0
R/W _{this register will be read for a pin configured as a}
4
PD4DT
0
R/W ^{general output port, while the state of the}
corresponding pin will be read for a pin configured as a
3
PD3DT
0
R/W _{general input port.}
2
PD2DT
0
R/W
1
PD1DT
0
R/W
0
PD0DT
0
R/W
Rev. 1.00 Oct. 01, 2007 Page 1724 of 1956
REJ09B0256-0100