SH7763 Datasheet, PDF (512/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
(MCLK)
MCLK
CKE
Command
MA9-0
MA13-11
MA10
BA1-0
T0 T1
REFA
REFA
ACT
t_RFC = 11 to 15 cycles
t_RFC = 11 to 15 cycles
Row
Row
Bank
MCS
MRAS
MCAS
MWE
Auto-refresh
Figure 12.13 Basic DDRIF Timing (Auto-Refresh (REFA) Enter/Exit to Bank Activate
(ACT))
Rev. 1.00 Oct. 01, 2007 Page 446 of 1956
REJ09B0256-0100