SH7205 Datasheet, PDF (999/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Bit 9: IRR9
0
1
Section 20 Controller Area Network (RCAN-TL1)
Description
No pending notification of message overrun/overwrite
[Clearing condition]
Clearing of all bit in UMSR/setting MBIMR for all UMSR set (initial value)
A receive message has been discarded due to overrun condition or a
message has been overwritten
[Setting condition]
Message is received while the corresponding RXPR and/or RFPR = 1 and
MBIMR = 0
Bit 8 - Mailbox Empty Interrupt Flag (IRR8): This bit is set when one of the messages set for
transmission has been successfully sent (corresponding TXACK flag is set) or has been
successfully aborted (corresponding ABACK flag is set). In Event Triggered mode the related
TXPR is also cleared and this mailbox is now ready to accept a new message data for the next
transmission. In Time Trigger mode TXPR for the Mailboxes from 30 to 24 is not cleared after a
successful transmission in order to keep transmitting at each programmed basic cycle. In effect,
this bit is set by an OR’ed signal of the TXACK and ABACK bits not masked by the
corresponding MBIMR flag. Therefore, this bit is automatically cleared when all the TXACK and
ABACK bits are cleared. It is also cleared by writing a ‘1’ to all the correspondent bit position in
MBIMR. Writing to this bit position has no effect.
Bit 8: IRR8
0
1
Description
Messages set for transmission or transmission cancellation request NOT
progressed. (Initial value)
[Clearing Condition]
All the TXACK and ABACK bits are cleared/setting MBIMR for all TXACK
and ABACK set
Message has been transmitted or aborted, and new message can be stored
(in TT mode Mailbox 24 to 30 can be programmed with a new message only
in case of abortion)
[Setting condition]
When a TXACK or ABACK bit is set (if related MBIMR = 0).
Rev. 1.00 Mar. 25, 2008 Page 967 of 1868
REJ09B0372-0100