SH7205 Datasheet, PDF (1244/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Note: ∗ The DEVSEL bit should be set while CSSTS is 0, PID is NAK, and SUREQ is 0.
The MXPS bit should be set while CSSTS is 0 and PID is NAK.
Before modifying these bits after modifying the PID bits for the DCP from BUF to NAK,
check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to
NAK by this module, checking PBUSY is not necessary.
When the function controller function is selected, the DEVSEL bit should be set to 0.
24.3.34 DCP Control Register (DCPCTR)
DCPCTR is a register that is used to confirm the buffer memory status, control setup transactions
and split transactions, change and confirm the data PID sequence bit, and set the response PID for
the DCP.
This register is initialized by a power-on reset. The CCPL and PID[2:0] bits are initialized by a
USB bus reset.
Bit: 15 14 13 12 11 10
BSTS
SUREQ CSCLR
CSSTS
SUREQ
CLR
—
Initial value: 0
0
0
0
0
-
R/W: R R/W*² R*¹/ R
W*²
R*¹/ R
W*²
Notes: 1. This bit is always read as 0.
2. Only 1 can be written to.
9
8
7
6
5
4
3
2
1
0
— SQCLR SQSET SQMON PBUSY PINGE — CCPL
PID[1:0]
-
0
0
1
R R*¹/ R*¹/ R
W*² W*²
0
0
-
0
0
0
R R/W R R/W R/W R/W
Bit
Bit Name
Initial
Value R/W
Description
15
BSTS
0
R
Buffer Status
Indicates whether DCP FIFO buffer access is
enabled or disabled. The direction of access,
reading or writing, is determined by the ISEL bit in
CFIFOSEL.
0: Buffer access is disabled.
1: Buffer access is enabled.
Rev. 1.00 Mar. 25, 2008 Page 1212 of 1868
REJ09B0372-0100