SH7205 Datasheet, PDF (117/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Instruction
FSUB DRm, DRn
FTRC FRm, FPUL
FTRC DRm, FPUL
Section 2 CPU
Instruction Code
1111nnn0mmm00001
1111mmmm00111101
1111mmm000111101
Operation
DRn-DRm → DRn
(long)FRm → FPUL
(long)DRm → FPUL
Compatibility
Execu-
tion
Cycles T Bit
SH2E SH4
6

Yes
1

Yes Yes
2

Yes
SH-2A/
SH2A-
FPU
Yes
Yes
Yes
2.4.9 FPU-Related CPU Instructions
Table 2.18 FPU-Related CPU Instructions
Instruction
LDS
Rm,FPSCR
LDS
Rm,FPUL
LDS.L @Rm+, FPSCR
LDS.L @Rm+, FPUL
STS
FPSCR, Rn
STS
FPUL,Rn
STS.L FPSCR,@-Rn
STS.L FPUL,@-Rn
Instruction Code
0100mmmm01101010
0100mmmm01011010
0100mmmm01100110
0100mmmm01010110
0000nnnn01101010
0000nnnn01011010
0100nnnn01100010
0100nnnn01010010
Compatibility
Operation
Execu-
tion
Cycles T Bit
SH2E SH4
SH-2A/
SH2A-
FPU
Rm → FPSCR
1

Yes Yes Yes
Rm → FPUL
1

Yes Yes Yes
(Rm) → FPSCR, Rm+=4 1

Yes Yes Yes
(Rm) → FPUL, Rm+=4 1

Yes Yes Yes
FPSCR → Rn
1

Yes Yes Yes
FPUL → Rn
1

Yes Yes Yes
Rn-=4, FPCSR → (Rn) 1

Yes Yes Yes
Rn-=4, FPUL → (Rn) 1

Yes Yes Yes
Rev. 1.00 Mar. 25, 2008 Page 85 of 1868
REJ09B0372-0100