SH7205 Datasheet, PDF (307/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
19 to 16 RRCV[3:0] 0000
R/W Post-Read Data Recovery Cycle Setting
These bits specify the number of data recovery cycles to
be inserted after read accesses to the external bus. If a
value other than 0 is selected, data recovery cycles are
inserted in the following cases:
If a read access to the external bus is followed by a write
access to the external bus. (Data recovery cycles are
inserted even when access is performed sequentially to
the same CSC channel.)
If a read access to the external bus is followed by a read
access to a different CSC channel. (No data recovery
cycles are inserted in cases of sequential read accesses
to the same CSC channel.)
Note that if idle cycles occur between accesses to the
external bus, the number of data recovery cycles
inserted is reduced by the number of idle cycles.
0000: 0 cycles
0001: 1 cycle
:
1111: 15 cycles
15 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Notes: 1. When accessing SDRAM, there is no danger of data collision on the bus due to timing.
Consequently, there is no data recovery cycle setting for SDRAM. (The value is fixed at
0 cycles.)
2. Writing to the CSn recovery cycle setting register (CSnREC) must be done while the
CSC for the corresponding channel is disabled (EXENB = 0). Only channel 0 (CS0) is
allowed for writing to the register without disabling the CSC (EXENB = 1). To write to
CS0REC with CSC enabled, satisfy all of the following conditions:
• Stop the DMAC.
• Keep the CPU other than the one that is going to rewrite the register from accessing
CS0 (including access for instruction fetch). For example, if CPU0 is going to rewrite
the register, make CPU1 stay looping by a program copied to on-chip memory, or put
CPU1 in a sleep state.
• Do not perform data write access to CS0 after a reset is released but before the
register is rewritten.
Rev. 1.00 Mar. 25, 2008 Page 275 of 1868
REJ09B0372-0100