SH7205 Datasheet, PDF (248/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.9 Register Banks and Bank Control Registers
(1) Banked Registers
The general registers (R0 to R14), global base register (GBR), multiply-and-accumulate registers
(MACH and MACL), procedure register (PR), and the interrupt vector offset are banked.
(2) Register Banks
This LSI has 15 register banks, bank 0 to bank 14. Register banks are queued in first-in last-out
(FILO) sequence. Saving takes place in order, beginning from bank 0, and restoration takes place
in the reverse order, beginning from the last bank saved to.
7.9.1 Bank Save and Restore Operations
(1) Saving to Bank
Figure 7.11 shows register bank save operation. The following operation is performed when the
CPU accepts an interrupt and the use of register banks is enabled for that interrupt.
a. Assume that the values of the bank number bits (BN) in the bank number registers (C0IBNR
and C1IBNR) are i before the interrupt is generated.
b. The values in registers R0 to R14, GBR, MACH, MACL, and PR, and the vector offset (IVO)
of the accepted interrupt are saved to bank i indicated by BN.
c. The BN value is incremented by 1.
+1
(c)
BN
Register banks
Bank 0
Bank 1
:
:
(a)
(b)
Bank i
Bank i + 1
:
:
Bank 14
Registers
R0 to R14
GBR
MACH
MACL
PR
VTO
Figure 7.11 Bank Save Operation
Figure 7.12 shows the timing for saving to a register bank. Saving to a register bank takes place
between the start of interrupt exception handling and the start of fetching the first instruction in the
exception service routine.
Rev. 1.00 Mar. 25, 2008 Page 216 of 1868
REJ09B0372-0100