SH7205 Datasheet, PDF (215/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.3.12 Interrupt Enable Control Registers (C0INTER, C1INTER)
C0INTER and C1INTER are 16-bit registers that control whether to enable or disable acceptance
of interrupt requests by processors CPU0 and CPU1. If the same bits in both registers C0INTER
and C1INTER are set to 0, the acceptance by CPU0 is enabled.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
NMIE UDIE SLPEE -
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: *
*
*
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
15
NMIE
*
R/W NMI Interrupt Enable
This bit selects whether to enable NMI interrupt request
inputs.
0: NMI interrupt request input is disabled.
1: NMI interrupt request input is enabled.
14
UDIE
*
R/W UDI Interrupt Enable
This bit selects whether to enable interrupt request inputs
from UDI.
0: Interrupt request input from UDI is disabled.
1: Interrupt request input from UDI is enabled.
13
SLPEE *
R/W Sleep Error Interrupt Enable
This bit selects whether to enable interrupt request inputs
for sleep errors.
0: Interrupt request input for sleep error is disabled.
1: Interrupt request input for sleep error is enabled.
12 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Note: * The initial value is 1 for C0INTER and 0 for C1INTER.
Rev. 1.00 Mar. 25, 2008 Page 183 of 1868
REJ09B0372-0100