SH7205 Datasheet, PDF (120/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 2 CPU
2.5 Processing States
The LSI has four CPU processing states: reset, dual-processor active, single-processor active, and
power-down. Figure 2.6 shows the transitions between the states.
Manual reset from any state
other than deep standby mode
Power-on reset from any state
other than deep standby mode
Manual reset state
Power-on reset state
NMI interrupt,
IRQ interrupt*, or
manual reset
Reset state
Interrupt request to CPU0 or CPU1
CPU1 executes
SLEEP instruction
Dual-processor
mode
Interrupt
Interrupt
request to CPU1 request to CPU0
NMI interrupt or
IRQ interrupt
CPU0 executes
SLEEP instruction
with STBY bit cleared
Dual-processor
active state
Single-processor 0
mode
CPU0 executes
SLEEP instruction
with STBY bit
cleared
CPU0 executes
SLEEP instruction
with STBY bit set
and DEEP bit cleared
Interrupt request
to CPU0
CPU1 executes
SLEEP instruction
Single-processor 1
mode
Interrupt request
to CPU1
CPU0 executes
SLEEP instruction
with STBY and DEEP
bits set
Single-processor
active state
Dual-sleep mode
Software standby mode
Deep standby mode
Power-down state
Note: * IRQ can be cancelled only by PC3 to PC0 or PJ3 to PJ0.
Figure 2.6 Transitions between Processing States
Rev. 1.00 Mar. 25, 2008 Page 88 of 1868
REJ09B0372-0100