SH7205 Datasheet, PDF (838/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 Synchronous Serial Communication Unit (SSU)
17.3.3 SS Mode Register (SSMR)
SSMR selects the MSB first/LSB first, clock polarity, clock phase, and clock rate of synchronous
serial communication.
Bit: 7
6
5
4
MLS CPOS CPHS -
Initial value: 0
0
0
0
R/W: R/W R/W R/W R
3
2
1
0
-
CKS[2:0]
0
0
0
0
R R/W R/W R/W
Initial
Bit
Bit Name Value R/W
7
MLS
0
R/W
6
CPOS
0
R/W
5
CPHS
0
R/W
4, 3 
All 0
R
Description
MSB First/LSB First Select
Selects that the serial data is transmitted in MSB first or
LSB first.
0: LSB first
1: MSB first
Clock Polarity Select
Selects the SSCK clock polarity.
0: High output in idle mode, and low output in active
mode
1: Low output in idle mode, and high output in active
mode
Clock Phase Select (Only for SSU Mode)
Selects the SSCK clock phase.
0: Data changes at the first edge.
1: Data is latched at the first edge.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 806 of 1868
REJ09B0372-0100