SH7205 Datasheet, PDF (255/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Figure 8.1 shows a block diagram of the UBC.
Section 8 User Break Controller (UBC)
Access
control
Internal bus
(I bus)
IDB IAB
CPU bus
(C bus)
CPU
memory
access bus
CPU
instruction
fetch bus
MDB MAB FAB
Access
comparator
Address
comparator
Data
comparator
Channel 0
Access
comparator
Address
comparator
Data
comparator
Channel 1
Control
BBR_0
BAR_0
BAMR_0
BDR_0
BDMR_0
I bus
BBR_1
BAR_1
BAMR_1
BDR_1
BDMR_1
BRCR
[Legend]
BBR: Break bus cycle register
BAR: Break address register
BAMR: Break address mask register
BDR: Break data register
BDMR: Break data mask register
BRCR: Break control register
User break interrupt request
UBCTRG pin output
Figure 8.1 Block Diagram of UBC (for One CPU)
Rev. 1.00 Mar. 25, 2008 Page 223 of 1868
REJ09B0372-0100