SH7205 Datasheet, PDF (1037/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 20 Controller Area Network (RCAN-TL1)
The following diagram shows the flow to follow to move RCAN-TL1 into sleep mode.
Halt Request
Sleep Mode
Sequence flow
Write MCR[1] = 1
GSR[4] = 1
Yes
IRR[0] = 1
Write IRR[0] = 1
IRR[0] = 0
Sleep Request
Write MCR[1] = 0 & MCR[5] = 1
IRR[0] = 1
Write IRR[0] = 1
IRR[0] = 0
Sleep Mode
CAN Bus Activity
Yes
IRR[12] = 1
MCR[7] = 1
Yes
MCR[5] = 0
Write IRR[12] = 1
IRR[12] = 0
No
User monitor
No
No
Write IRR[12] = 1
IRR[12] = 0
Write MCR[5] = 0
: Hardware operation
: Manual operation
CLK is
STOP
Only MCR, GSR,
IRR, IMR can be
accessed.
No
GSR4 = 0
Yes
Transmission/Reception Mode
User monitor
Rev. 1.00 Mar. 25, 2008 Page 1005 of 1868
REJ09B0372-0100