SH7205 Datasheet, PDF (937/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
Initial
Bit
Bit Name Value R/W Description
0
RDF
0
R(/W)* Receive Data Full
Indicates that, when the FIFO is operating for reception,
the received data is transferred to the FIFO data
register (SSIFDR) and the number of data bytes in the
FIFO data register has become greater than the receive
trigger number specified by RTRG[1:0] in the FIFO
control register (SSIFCR).
0: Number of received data bytes in SSIFDR is less
than the set receive trigger number.
[Clearing conditions]
• Power-on reset
• “0” is written to RDF after data is read from SSIFDR
until the number of data bytes in SSIFDR becomes
less than the set receive trigger number.
• The DMAC is activated by receive data full (RXI)
interrupt, and data is read from SSIFDR until the
number of data bytes in SSIFDR becomes less than
the set receive trigger number.
1: Number of received data bytes in SSIFDR is equal to
or greater than the set receive trigger number.
[Setting condition]
• Data of the number of bytes that is equal to or
greater than the set receive trigger number is stored
in SSIFDR.*¹
Note: *1 Since SSIFDR is an 8-stage FIFO register,
the amount of data that can be read from it
while RDF = 1 is the set receive trigger
number of bytes at maximum.
Continuing to read data from SSIFDR after
reading all the data will result in lack of data.
The number of data bytes in SSIFDR is
indicated in the DC bits in SSIFSR.
Note: * The bit can be read or written to. Writing 0 initializes the bit, but writing 1 is ignored.
Rev. 1.00 Mar. 25, 2008 Page 905 of 1868
REJ09B0372-0100