SH7205 Datasheet, PDF (1372/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
26.3.4 Interrupt Status Register for Graphics (GR_IRSTAT)
The register GR_IRSTAT indicates the interrupt state of the 2DG. When an interrupt event
corresponding to the IRQ_DEMPT, IRQ_ASHFUL, IRQ_DHFUL, or IRQ_SHFUL bit in this
register occurs, the given bit will be set as long as the event has not been masked by the
MSK_DEMPT, MSK_ASHFUL, MSK_DHFUL, or MSK_SHFUL bit in the GR_INTMSK
register. For the other bits in register GR_IRSTAT, the bit will be set to "1" when the
corresponding event occurs, regardless of the setting in the interrupt mask control register for
graphics (GR_INTMSK). For details on interrupts, see section 26.4.5, Interrupts.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
IRQ_
DEMPT
-
IRQ_ IRQ_ IRQ_
ASHFUL DHFUL SHFUL
-
-
-
-
Initial value: -
-
-
-
-
-
-
0
-
0
0
0
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
INT_ INT_ INT_
VSYC UDFL FILD
-
-
-
INT_
DEMPT
-
INT_ INT_ INT_
ASHFUL DHFUL SHFUL
-
-
-
INT_
GR
Initial value: -
0
0
0
-
-
-
0
-
0
0
0
-
-
-
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
Bit name
31 to 25 
Initial
Value
R/W
Undefined R
24
IRQ_DEMPT 0
R
23

Undefined R
Description
Reserved
The read value is undefined.
Input Buffer E Full Flag for the Output Block
This bit indicates that the input buffer E for the output
block is full.
0: Input buffer E for the output block is not full.
1: Input buffer E for the output block is full.
[Clearing condition]
• Writing 1 to the DIS_DEMPT bit of register
GR_INTDIS.
[Setting condition]
• Input buffer E for the output block is full.
Reserved
The read value is undefined.
Rev. 1.00 Mar. 25, 2008 Page 1340 of 1868
REJ09B0372-0100