SH7205 Datasheet, PDF (575/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT_0 value
TGRB_0
TGRA_0
H'0000
H'0200
H'0450
H'0520
Time
TGRC_0 ^H'0200
TGRA_0
H'0200
H'0450
Transfer
H'0450
H'0520
H'0520
TIOCA
Figure 12.19 Example of Buffer Operation When TCNT_0 Clearing is Selected for
TGRC_0 to TGRA_0 Transfer Timing
12.4.4 Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 counter clock upon overflow/underflow of
TCNT_2 as set in bits TPSC0 to TPSC2 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 12.42 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the
counters operates independently in phase counting mode.
Table 12.42 Cascaded Combinations
Combination
Channels 1 and 2
Upper 16 Bits
TCNT_1
Lower 16 Bits
TCNT_2
For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional
input capture input pins can be specified by the input capture control register (TICCR). For input
capture in cascade connection, refer to section 12.7.22, Simultaneous Capture of TCNT_1 and
TCNT_2 in Cascade Connection.
Rev. 1.00 Mar. 25, 2008 Page 543 of 1868
REJ09B0372-0100