SH7205 Datasheet, PDF (86/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 2 CPU
Table 2.4 T Bit
SH-2A CPU
CMP/GE R1,R0
BT
TRGET0
BF
TRGET1
ADD
CMP/EQ
BT
#−1,R0
#0,R0
TRGET
Description
Example of Other CPU
T bit is set when R0 ≥ R1.
CMP.W R1,R0
The program branches to TRGET0 BGE
when R0 ≥ R1 and to TRGET1
BLT
when R0 < R1.
TRGET0
TRGET1
T bit is not changed by ADD.
SUB.W #1,R0
T bit is set when R0 = 0.
BEQ TRGET
The program branches if R0 = 0.
(10) Immediate Data
Byte immediate data is located in an instruction code. Word or longword immediate data is not
located in instruction codes but in a memory table. The memory table is accessed by an immediate
data transfer instruction (MOV) using the PC relative addressing mode with displacement.
With the SH-2A, 17- to 28-bit immediate data can be located in an instruction code. However, for
21- to 28-bit immediate data, an OR instruction must be executed after the data is transferred to a
register.
Table 2.5 Immediate Data Accessing
Classification SH-2A CPU
Example of Other CPU
8-bit immediate MOV
#H'12,R0
MOV.B #H'12,R0
16-bit immediate MOVI20
#H'1234,R0
MOV.W #H'1234,R0
20-bit immediate MOVI20
#H'12345,R0
MOV.L #H'12345,R0
28-bit immediate MOVI20S #H'12345,R0
MOV.L #H'1234567,R0
OR
#H'67,R0
32-bit immediate MOV.L
@(disp,PC),R0
MOV.L #H'12345678,R0
.................
.DATA.L H'12345678
Note: @(disp, PC) accesses the immediate data.
Rev. 1.00 Mar. 25, 2008 Page 54 of 1868
REJ09B0372-0100