SH7205 Datasheet, PDF (282/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Cache
Table 9.3 Way to Be Replaced When a Cache Miss Occurs in PREF Instruction
LE
W3LOAD* W3LOCK W2LOAD* W2LOCK Way to Be Replaced
0
×
×
×
×
Decided by LRU (table 9.1)
1
×
0
×
0
Decided by LRU (table 9.1)
1
×
0
0
1
Decided by LRU (table 9.5)
1
0
1
×
0
Decided by LRU (table 9.6)
1
0
1
0
1
Decided by LRU (table 9.7)
1
0
×
1
1
Way 2
1
1
1
0
×
Way 3
[Legend] x: Don't care
Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time.
Table 9.4 Way to Be Replaced When a Cache Miss Occurs in Other Than PREF
Instruction
LE
W3LOAD* W3LOCK W2LOAD* W2LOCK Way to Be Replaced
0
×
×
×
×
Decided by LRU (table 9.1)
1
×
0
×
0
Decided by LRU (table 9.1)
1
×
0
×
1
Decided by LRU (table 9.5)
1
×
1
×
0
Decided by LRU (table 9.6)
1
×
1
×
1
Decided by LRU (table 9.7)
[Legend] x: Don't care
Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time.
Rev. 1.00 Mar. 25, 2008 Page 250 of 1868
REJ09B0372-0100