SH7205 Datasheet, PDF (1626/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 31 User Debugging Interface (H-UDI)
Bit
7 to 2
Bit Name

Initial
Value
All 1
1

0
0

1
R/W Description
R
Reserved
These bits are always read as 1.
R
Reserved
These bits are always read as 0.
R
Reserved
These bits are always read as 1.
Table 31.6 Supported Commands for Emulation TAP Controller
Bits 15 to 8
TI7 TI6 TI5 TI4 TI3 TI2 TI1 TI0 Description
0
1
1
0




H-UDI reset negation
0
1
1
1




H-UDI reset assertion
1
0
0
1
1
1
0
0
TDO transition timing switch
1
0
1
1




H-UDI interrupt
Other than the above
Reserved
Rev. 1.00 Mar. 25, 2008 Page 1594 of 1868
REJ09B0372-0100