SH7205 Datasheet, PDF (202/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
Register Name
DMA transfer request enable
register 5
DMA transfer request enable
register 6
DMA transfer request enable
register 7
DMA transfer request enable
register 8
Abbreviation R/W
DREQER5 R/W
Initial
Value
H'00
Address
Access Size
H'FFFE0805 8
DREQER6 R/W H'00 H'FFFE0806 8, 16
DREQER7 R/W H'00 H'FFFE0807 8
DREQER8 R/W H'00 H'FFFE0808 8
7.3.1
Interrupt Priority Registers 01, 02, 05 to 21 (C0IPR01, C0IPR02, C0IPR05 to
C0IPR21, C1IPR01, C1IPR02, C1IPR05 to C1IPR21)
C0IPR01, C0IPR02, and C0IPR05 to C0IPR21 and C1IPR01, C1IPR02, and C1IPR05 to
C0IPR21 are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for
IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts. Table 7.5 shows the
correspondence between the interrupt request sources and the bits in C0IPR01, C0IPR02, and
C0IPR05 to C0IPR21 and C1IPR01, C1IPR02, and C1IPR05 to C0IPR21.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Mar. 25, 2008 Page 170 of 1868
REJ09B0372-0100