SH7205 Datasheet, PDF (1194/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name Value
R/W
12
DREQE
0
R/W
11, 10 MBW[1:0] 00
R/W
9

Undefined R
8
BIGEND
0
R/W
Description
DMA Transfer Request Enable
Enables or disables generation of DMA transfer
requests.
0: Request disabled
1: Request enabled
Note: To enable the DMA transfer request, set the
CURPIPE bits first, then set this bit to 1.
Before modifying the CURPIPE bit setting,
this bit must be cleared to 0.
FIFO Port Access Bit Width
Specifies the bit width for accessing the DnFIFO
port.
00: 8-bit width
01: 16-bit width
10: 32-bit width
11: Setting prohibited
Once reading of data from the buffer memory is
started, the FIFO port access bit width cannot be
modified until all the data has been read.
When the selected pipe is in the receiving direction,
set the CURPIPE and MBW bits simultaneously.
For details, refer to section 24.4.4, FIFO Buffer.
The bit width cannot be changed from the 8-bit
width to the 16-/32-bit width or from the 16-bit width
to the 32-bit width while data is being written to the
buffer memory.
Reserved
Undefined value is read from this bit. The write
value should always be 0.
FIFO Port Endian Control
Specifies the byte endian for the DnFIFO port.
0: Little endian
1: Big endian
Rev. 1.00 Mar. 25, 2008 Page 1162 of 1868
REJ09B0372-0100