SH7205 Datasheet, PDF (1379/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
Bit
4
3 to 1
0
Initial
Bit name Value
R/W
MSK_SHFUL 1
R/W

Undefined R
MSK_GR 1
R/W
Description
Blitter Input Buffer B Full Interrupt Mask
This bit masks an input buffer B full interrupt for the
blitter.
0: Enables an input buffer B full interrupt for the
blitter.
1: Masks an input buffer B full interrupt for the blitter.
Reserved
The read value is undefined. The write value should
always be 0.
Blitter Operation Completion Interrupt Mask
This bit masks a blitter operation completion
interrupt.
0: Enables a blitter operation completion interrupt.
1: Masks a blitter operation completion interrupt.
• Note that the MGR_MIXHTMG, MGR_MIXHS, and MGR_MIXVTMG registers should be
set according to the display panel to be used before the interrupts masked by the MSK_UDFL
and MSK_FILD bits are cancelled.
Rev. 1.00 Mar. 25, 2008 Page 1347 of 1868
REJ09B0372-0100