SH7205 Datasheet, PDF (1431/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
(1) VICLK = 27 MHz synchronous system
VIVSYNC
VICLKENB
Moving picture
data
FIELD (Reference)
VLDPV line = 240
WPV + PDPV
240 lines
Same as the number of
lines set by the VLDPV bits
EVEN
VS_ext
240 lines
ODD
(2) DCLKIN =
approx. 8 MHz
synchronous system
(WQVGA)
The priod varies within 1H at most
since VIVSYNC is latched
in synchronization with HSYNC_dck.
VSYNC_dck
(Internal)
WPV bits
Reading synthesized
output data from
the data buffer
VLDPV = 240 lines
PDPV bits VLDPV bits
VS_ext
VLDPV = 240 lines
When moving picture is not input, the timing chart for the VICLK system shown in (1) is not applicable.
Only graphic data is output in synchronization with VSYNC_dck set in the register.
Figure 26.13 Timing in the Vertical Direction
(with Moving Pictures Supplied)
DCLKIN
CSYNC
Synthesized data
(RGB data)
D0
D1
D2
Synthesized data and the CSYNC signal are synchronous with the rising edge of DCLKIN (for both NTSC/PAL).
Figure 26.14 2DG Output Signals and DCLKIN
Rev. 1.00 Mar. 25, 2008 Page 1399 of 1868
REJ09B0372-0100