SH7205 Datasheet, PDF (1101/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
(6) Data Error
• When a program error or erase error occurs, the error is reflected on the error source flags.
Interrupts for each source can be specified.
• When a read error occurs, an ECC in the control code is other than 0. This read error is
reflected on the ECC error source flag.
• When an ECC error occurs, perform an error correction, specify another sector to be replaced,
and copy the contents of the block to another sector as required.
(7) Data Transfer FIFO and Data Register
• The 224-byte data FIFO register (FLDTFIFO) is incorporated for data transfer of flash
memory.
• The 32-byte control code FIFO register (FLECFIFO) is incorporated for data transfer of
control code.
(8) DMA Transfer
• By individually specifying the destinations of data and control code of flash memory to the
DMA controller, data and control code can be sent to different areas.
(9) Access Time
• The operating clock (FCLK) on the pins for the AND-/NAND-type flash memory is generated
by dividing the peripheral clock (Pφ). The division ratio can be specified by the FCKSEL and
QTSEL bits in the common control register (FLCMNCR).
• Before changing the CPG configuration, the FLCTL must be placed in a module stop state.
• In NAND-type flash memory, the FSC and FWE pins operate at the frequency of FCLK. In
AND-type flash memory, the FSC pin operates at the frequency of FCLK and the FWE pin
operates at half the FCLK frequency. These operating frequencies must be specified within the
maximum operating frequency of memory to be connected.
Rev. 1.00 Mar. 25, 2008 Page 1069 of 1868
REJ09B0372-0100