SH7205 Datasheet, PDF (465/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.5 DMA Transfer End and Interrupts
11.5.1 DMA Transfer End
When the value in the DMA current byte count register (DMCBCTn) becomes H'000 0000
(transfer end of all data), the DMA transfer end condition is satisfied and one DMA transfer ends.
The following describes the operations performed when the DMA transfer end condition is
detected.
• DMA transfer end detection
The DMA transfer end condition detect bit (DEDET) of the channel corresponding to the
DMA transfer end detection register (DMEDET) is set to 1.
• Interrupt request generation
An interrupt request is generated for the interrupt controller according to the settings of the
DMA interrupt control register (DMICNT) and the DMA common interrupt control register
(DMICNTA).
• DMA end signal output
The DMA end signal (DMATC_N) is output according to the setting of the DMA end signal
output control bit (DTCM) of the DMA mode register (DMMODn).
• DMA transfer enable bit (DEN) clearing
If the DMA transfer enable clear bit (ECLR) of DMA control register B (DMCNTBn) is set to
1, the DEN bit of DMA control register B (DMCNTBn) is cleared to 0 and the subsequent
DMA transfer of the channel is suspended.
If the DMA transfer enable clear bit (ECLR) is cleared to 0, the DEN bit is not cleared.
• Source address register reloading
If the DMA source address reload function enable bit (SRLOD) of DMA control register A
(DMCNTAn) is set to 1, the value in the DMA reload source address register (DMRSADRn)
is reloaded to the DMA current source address register (DMCSADRn).
• Destination address register reloading
If the DMA destination address reload function enable bit (DRLOD) of DMA control register
A (DMCNTAn) is set to 1, the value in the DMA reload destination address register
(DMRDADRn) is reloaded to the DMA current destination address register (DMCDADRn).
• Byte count register reloading
If the DMA byte count reload function enable bit (BRLOD) of DMA control register A
(DMCNTAn) is set to 1, the value in the DMA reload byte count register (DMRBCTn) is
reloaded to the DMA current byte count register (DMCBCTn).
Rev. 1.00 Mar. 25, 2008 Page 433 of 1868
REJ09B0372-0100