SH7205 Datasheet, PDF (1215/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name Value
R/W Description
3
VALID
0
R/W*² USB Request Reception*⁶
This bit indicates whether reception of a USB request
is detected or not.
0: Not detected
1: Setup packet received
2 to 0 CTSQ[2:0] 000
R
Control Transfer Stage
These bits indicate the state of the control transfer
stage.
000: Idle or setup stage
001: Control read data stage
010: Control read status stage
011: Control write data stage
100: Control write status stage
101: Control write (no data) status stage
110: Control transfer sequence error
111: Setting prohibited
Notes: 1. DVST is initialized to 0 and DVSQ[2:0] to 000 by a power-on reset.
DVST is initialized to 1 and DVSQ[2:0] to 001 by a USB bus reset.
2. Only 0 can be written to.
3. To clear the VBINT, RESM, SOFR, DVST, or CTRT bit, write 0 only to the bits to be
cleared; write 1 to the other bits. Do not write 0 to the status bits indicating 0.
4. This module detects the changes in the statuses indicated by the VBINT and RESM bits
even while the clock supply is stopped (while SCKE is 0), and outputs the
corresponding interrupt requests as long as they are enabled. Clearing the status
should be done after enabling the clock supply.
5. Transitions in the status of the RESM, DVST, and CTRT bits only occur when the
function controller function is selected; clear the corresponding interrupt enable bits to 0
(disable) when the host controller function is selected.
6. The DVSQ, VALID, and CTRQ bits are valid when the function controller function is
selected
Rev. 1.00 Mar. 25, 2008 Page 1183 of 1868
REJ09B0372-0100