SH7205 Datasheet, PDF (978/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 20 Controller Area Network (RCAN-TL1)
Important: Please note that the TimeStamp is stored in a temporary register. Only after a
successful transmission or reception the value is then copied into the related Mailbox field. The
TimeStamp may also be updated if the CPU clears RXPR[N]/RFPR[N] at the same time that
UMSR[N] is set in overrun, however it can be read properly before clearing RXPR[N]/RFPR[N].
(5) Tx-Trigger Time (TTT) and Time Trigger control
For Mailbox-29 to 24, when MBC is set to 000 (Bin) in time trigger mode (CMAX!= 3'b111), Tx-
Trigger Time works as Time_Mark to determine the boundary between time windows. The TTT
and TT control are comprised of two 16-bit read/write areas as follows. Mailbox-30 doesn't have
TT control and works as Time_Ref.
Mailbox 30 to 24 can be used for reception if not used for transmission in TT mode. However they
cannot join the event trigger transmission queue when the TT mode is used.
• Tx-Trigger Time
Bit: 15 14 13 12 11 10 9
TTT15 TTT14 TTT13 TTT12 TTT11 TTT10 TTT9
Initial value: 0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W
8
TTT8
0
R/W
7
TTT7
0
R/W
6
TTT6
0
R/W
5
TTT5
0
R/W
4
TTT4
0
R/W
3
TTT3
0
R/W
2
TTT2
0
R/W
1
TTT1
0
R/W
0
TTT0
0
R/W
• Time Trigger control
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TTW[1:0]
Offset[5:0]
0
0
0
0
0
rep_factor[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
R
R R/W R/W R/W
The following figure shows the differences between all Mailboxes supporting Time Triggered
mode.
Rev. 1.00 Mar. 25, 2008 Page 946 of 1868
REJ09B0372-0100