SH7205 Datasheet, PDF (1605/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 30 Power-Down Modes
(b) Canceling by a reset
Dual-sleep mode is canceled and the reset exception handling is executed by a power-on reset or
manual reset, and then the LSI enters dual-processor mode.
30.3.5 Software Standby Mode
(1) Transition to Software Standby Mode
In single-processor 0 mode where only CPU0 is running, the LSI can enter software standby
mode.
After confirming that the SLEEP bit in C1MSR is 1, when CPU0 executes the SLEEP instruction
with the STBY bit set to 1 and the DEEP bit cleared to 0 in STBCR1, the LSI switches from a
program execution state to software standby mode. However, if CPU0 executes the SLEEP
instruction when the SLPERE bit in STBCR1 is 1, the LSI does not enter software standby mode
and a sleep error exception occurs.
In software standby mode, not only CPU0 and CPU1 but also the clock and on-chip peripheral
modules halt. The clock output from the CKIO pin also stops.
The contents of the CPU0/CPU1 registers and the cache registers remain unchanged. Some
registers of on-chip peripheral modules are, however, initialized. As for the states of on-chip
peripheral module registers in software standby mode, see section 32.3, Register States in Each
Operating Mode.
The CPU takes one cycle to finish writing to STBCR1, and then executes processing for the next
instruction. However, it takes one or more cycles to actually write. Therefore, execute a SLEEP
instruction after reading STBCR1 to have the values written to STBCR1 by the CPU to be
definitely reflected in the SLEEP instruction.
The procedure for switching to software standby mode is as follows:
1. Clear the TME bit in the WDT0 timer control/status register (WTCSR0) to 0 to stop the WDT.
2. Set the WDT0 timer counter (WTCNT0) to 0 and set the clock select bits CKS[2:0] in
WTCSR0 to appropriate values to secure the specified oscillation settling time.
3. After setting the STBY bit to 1 and DEEP bit to 0 in STBCR1, read STBCR1.
4. Setting to disable an interrupt to CPU1 and confirming that the SLEEP bit in C1MSR is 1, and
then make CPU0 to execute the SLEEP instruction.
Rev. 1.00 Mar. 25, 2008 Page 1573 of 1868
REJ09B0372-0100