SH7205 Datasheet, PDF (1080/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 21 A/D Converter (ADC)
6. The ADST bit is not cleared automatically, so steps 2. to 4. are repeated as long as the ADST
bit remains set to 1. When steps 2. to 4. are repeated, the ADF flag is kept to 1. When the
ADST bit is cleared to 0, A/D conversion stops. The ADF bit is cleared by reading ADF while
ADF = 1, then writing 0 to the ADF bit.
If both the ADF flag and ADIE bit are set to 1 while steps 2. to 4. are repeated, an ADI interrupt is
requested at all times. To generate an interrupt on completing conversion of the third channel,
clear the ADF bit to 0 after an interrupt is requested.
Rev. 1.00 Mar. 25, 2008 Page 1048 of 1868
REJ09B0372-0100