SH7205 Datasheet, PDF (1338/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 AT Attachment Packet Interface (ATAPI)
Initial
Bit
Bit Name Value R/W Description
2
R/W
0
R/W This bit controls which to perform, FIFO read or write.
1: FIFO read (DMA transfer data-in operation)
0: FIFO write (DMA transfer data-out operation)
To read data from an ATAPI device, set the bit to 1.
To write data to an ATAPI device, clear the bit to 0.
1
STOP
0
R/W This bit forcibly terminates a DMA transfer.
[Write]
0: Ignored.
1: A data transfer is forcibly terminated.
[Read]
0: No forced termination command is issued.
1: A forced data transfer termination command is
issued.
The bit is cleared to 0 when the next DMA transfer
starts.
Note: No transfer can be restarted from the address
at which a DMA transfer was forcibly
terminated.
0
START
0
R/W This bit causes a DMA transfer to start.
If the bit is set to 1, a DMA transfer is started. If it is
cleared to 0, it is ignored.
[Write]
0: Ignored.
1: A DMA transfer is started.
[Read]
0: DMA transfer inactive.
1: Busy, performing a DMA transfer.
Note: The task file register must not be accessed
while DMA is active.
Rev. 1.00 Mar. 25, 2008 Page 1306 of 1868
REJ09B0372-0100