SH7205 Datasheet, PDF (1197/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name Value
R/W Description
14
BCLR
0
R/W*² CPU Buffer Clear
This bit should be set to 1 to clear the FIFO buffer on
the CPU side for the specified pipe.
Of the FIFO buffers assigned to the specified pipe,
the one on the CPU side is cleared.
When double buffer mode is set for the FIFO buffer
assigned to the specified pipe, this module clears
only one plane of the FIFO buffer even when both
planes are read-enabled. When the specified pipe is
in the transmitting direction, if 1 is written to BVAL
and BCLR bits simultaneously, this module clears
the data that was written before, enabling
transmission of a zero-length packet.
0: Invalid
1: Clears the buffer memory on the CPU side.
Note: When the specified pipe is the DCP, setting
BCLR to 1 allows this module to clear the FIFO
buffer regardless of whether the FIFO buffer is
on the CPU side or SIE side. To clear the
buffer on the SIE side, set the PID bits for the
DCP to NAK before setting BCLR to 1.
When the specified pipe is not the DCP, writing
1 to this bit should be done while FRDY
indicates 1 (set by this module).
13
FRDY
0
R
FIFO Port Ready
Indicates whether the FIFO port is accessible.
In the following cases, FRDY is set to 1 but data
cannot be read via the FIFO port because there is no
data to be read. In these cases, set BCLR to 1 to
clear the FIFO buffer to enable transmission and
reception of the next data.
• A zero-length packet is received when the FIFO
buffer assigned to the specified pipe is empty.
• A short packet is received and the data is
completely read while BFRE is 1.
0: FIFO port access is disabled.
1: FIFO port access is enabled.
Rev. 1.00 Mar. 25, 2008 Page 1165 of 1868
REJ09B0372-0100