SH7205 Datasheet, PDF (891/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 18 I²C Bus Interface 3 (IIC3)
18.3.10 NF2CYC Register (NF2CYC)
NF2CYC is an 8-bit readable/writable register that selects the range of the noise filtering for the
SCL and SDA pins. For details of the noise filter, see section 18.4.7, Noise Filter.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
-
-
PRS
NF2
CYC
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W
Bit
7 to 2
1
0
Bit Name

PRS
NF2CYC
Initial
Value
All 0
0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Pulse Width Ratio Select
Specifies the ratio of the high-level period to the low-
level period for the SCL signal.
0: The ratio of high to low is 0.5 to 0.5.
1: The ratio of high to low is about 0.4 to 0.6.
R/W Noise Filtering Range Select
0: The noise less than one cycle of the peripheral clock
can be filtered out
1: The noise less than two cycles of the peripheral clock
can be filtered out
Rev. 1.00 Mar. 25, 2008 Page 859 of 1868
REJ09B0372-0100